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| MC74VHC138 3- -8 Line Decoder -toThe MC74VHC138 is an advanced high speed CMOS 3- -8 -todecoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 - A2) determine which one of the outputs (Y0 - Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. http://onsemi.com MARKING DIAGRAMS 16 9 SOIC-16 D SUFFIX CASE 751B VHC138 AWLYYWW 1 8 16 9 * * * * * * * * * * * * High Speed: tPD = 5.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 122 FETs or 30.5 Equivalent Gates These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative. TSSOP-16 DT SUFFIX CASE 948F VHC 138 AWLYWW 1 8 16 9 SOIC EIAJ-16 M SUFFIX CASE 966 A WL YY WW A WL Y WW VHC138 ALYW 1 8 = Assembly Location = Wafer Lot = Year = Work Week A L Y W = Assembly Location = Wafer Lot = Year = Work Week = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC74VHC138D MC74VHC138DR2 MC74VHC138DT Package SOIC--16 SOIC--16 TSSOP--16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel 48 Units/Rail 2000 Units/Reel MC74VHC138DTR2 TSSOP--16 MC74VHC138M MC74VHC138MEL SOIC EIAJ--16 SOIC EIAJ--16 (c) Semiconductor Components Industries, LLC, 2006 March, 2006 - Rev. 4 - 1 Publication Order Number: MC74VHC138/D MC74VHC138 PIN ASSIGNMENT A0 A1 A2 E1 E2 E3 Y7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 FUNCTION TABLE Inputs E3 X X L H H H H H H H H E2 X H X L L L L L L L L H X X L L L L L L L L X X X L L L L H H H H X X X L L H H L L H H X X X L H L H L H L H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H Outputs H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L ENABLE INPUTS SELECT INPUTS A0 A1 A2 1 2 3 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LOGIC DIAGRAM 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 ACTIVE--LOW OUTPUTS E3 E2 E1 6 5 4 H = high level (steady state); L = low level (steady state); X = don't care http://onsemi.com 2 MC74VHC138 EXPANDED LOGIC DIAGRAM 15 Y0 14 Y1 A0 1 13 Y2 A1 2 12 Y3 A2 3 11 Y4 10 E2 E1 5 4 9 Y5 Y6 7 Y7 E3 6 IEC LOGIC DIAGRAM A0 A1 A2 1 2 3 BIN/OCT 1 2 4 & E3 E2 E1 6 5 4 EN 0 1 2 3 4 5 6 7 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 E3 E2 E1 6 5 4 & A0 A1 A2 1 2 3 DMUX 0 2 0 G 7 0 1 2 3 4 5 6 7 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 http://onsemi.com 3 MC74VHC138 MAXIMUM RATINGS* Symbol VCC Vin Vout IIK IOK Iout ICC PD Tstg DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package Parameter Value - 0.5 to + 7.0 - 0.5 to + 7.0 - 0.5 to VCC + 0.5 -- 20 20 25 75 500 450 - 65 to + 150 Unit V V V mA mA mA mA mW _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin Vout TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.3V 0.3V VCC =5.0V 0.5V Parameter Min 2.0 0 0 -- 55 0 0 Max 5.5 5.5 VCC + 125 100 20 Unit V V V _C ns/V The JA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C 1 1 10 1000 Figure 1. Failure Rate vs. Time Junction Temperature http://onsemi.com 4 MC74VHC138 DC ELECTRICAL CHARACTERISTICS Symbol VIH Parameter Minimum High--Level Input Voltage Test Conditions VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 VIN = VIH or VIL IOH = -- 50 A VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 A VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = 5.5 V or GND VIN = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 0 to 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 2.0 3.0 4.5 TA = 25C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 40.0 Typ Max TA = 85C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.34 3.66 0.1 0.1 0.1 0.52 0.52 1.0 40.0 A A V Max TA = 125C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 Max Unit V VIL Maximum Low--Level Input Voltage Minimum High--Level Output Voltage VIN = VIH or VIL V VOH V IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbo l tPLH, tPHL TA = 25C Parameter Maximum Propagation Delay, A to Y Test Conditions VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF Min Typ 8.2 10.0 5.7 7.2 8.1 10.6 5.6 7.1 8.2 10.7 5.8 7.3 4 Max 11.4 15.8 8.1 10.1 12.8 16.3 8.1 10.1 11.4 14.9 8.1 10.1 10 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.5 18.0 9.5 11.5 15.0 18.5 9.5 11.5 13.5 17.0 9.5 11.5 10 TA = - 55 to 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.5 18.0 9.5 11.5 15.0 18.5 9.5 11.5 13.5 17.0 9.5 11.5 10 pF ns ns Unit ns tPLH, tPHL Maximum Propagation Delay, E3 to Y tPLH, tPHL Maximum Propagation Delay, E2 or E1 to Y CIN Maximum Input Capacitance Typical @ 25C, VCC = 5.0V 34 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no--load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 5 MC74VHC138 SWITCHING WAVEFORMS VALID A tPLH Y 50% VCC 50% tPHL Y VALID VCC GND E3 tPHL 50% VCC 50% tPLH VCC GND Figure 2. Figure 3. TEST POINT VCC 50% tPHL Y 50% VCC tPLH GND DEVICE UNDER TEST OUTPUT CL* E2 or E1 *Includes all probe and jig capacitance Figure 4. Figure 5. Test Circuit INPUT Figure 6. Input Equivalent Circuit http://onsemi.com 6 MC74VHC138 PACKAGE DIMENSIONS D SUFFIX SOIC CASE 751B-05 ISSUE J 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 --A16 --B1 8 P 8 PL 0.25 (0.010) M B S G F K C --TSEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DT SUFFIX TSSOP CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 2X L/2 J1 B --USECTION N-N J L PIN 1 IDENT. 1 8 N 0.15 (0.006) T U S 0.25 (0.010) M A --VN F DETAIL E C 0.10 (0.004) - - SEATING -TPLANE --W- D G H DETAIL E http://onsemi.com 7 MC74VHC138 PACKAGE DIMENSIONS M SUFFIX SOIC EIAJ-16 CASE 966-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 16 9 LE Q1 E HE M_ L DETAIL P 1 8 Z D A VIEW P c e b 0.13 (0.005) M A1 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.78 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800--282--9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082--1312 USA Phone: 480--829--7710 or 800--344--3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2--9--1 Kamimeguro, Meguro--ku, Tokyo, Japan 153--0051 Fax: 480--829--7709 or 800--344--3867 Toll Free USA/Canada Phone: 81--3--5773--3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74VHC138/D |
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